Samsung’s backside power delivery network (BSPDN) roadmap

Samsung has started providing more details about its backside power delivery network (BSPDN) roadmap, stating that its 2-nm process node will be optimized for this new technology when it enters mass production in 2027.

While trade media has been regularly reporting on the availability of BSPDN technology from large fabs—Intel, Samsung, and TSMC—according to TrendForce, it’s the first time a senior Samsung Foundry executive has provided details about the company’s BSPDN roadmap.

Source: Samsung

In a report published in Korea Economic Daily, Lee Sung-Jae, VP of PDK development team at Samsung, said that BSPDN will reduce the size of Samsung’s 2 nm chip by 17% compared to the traditional front-end power delivery. He added that BSPDN will allow Samsung to improve 2-nm chip’s performance and power efficiency by 8% and 15%, respectively.

According to an Intel study, power lines typically occupy around 20% of the space on the chip surface in a traditional front-end power delivery. The BSPDN technology puts the power rails on the back of the wafer to remove bottlenecks between power and signal lines, making the manufacturing of smaller chips easier.

Moreover, backside power delivery facilitates thicker, lower-resistance wires, thus delivering more power to enable higher performance and save power. According to a Samsung paper presented at the VLSI Symposium in 2023, BSPDN also facilitates a 9.2% reduction in wiring length.

In that paper, Samsung also claimed to have implemented backside power delivery in two Arm-based test chips, achieving a 10% and 19% die area reduction. The company didn’t disclose the process node for these test chips.

It’s worth noting that after being a pioneer in deploying gate-all-around (GAA) manufacturing technology in its 3-nm chips, Samsung is now following Intel and TSMC in implementing the BSPDN technique.

Intel, which calls its backside power delivery technology PowerVia, is expected to produce chips based on this technique this year. Next, TSMC is planning to integrate its backside power delivery technology—Super PowerRail architecture—in its 1.6 chips to be mass-produced in 2026.

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