Partners demo PCIe 6.0 64-GT/s interoperability
Alphawave Semi and Keysight joined forces to accelerate PCIe 6.0 compliance testing and bolster interconnectivity across AI compute infrastructure. The companies demonstrated interoperability between Alphawave’s PCIe 6.0 PHY and controller subsystem and Keysight’s PCIe 6.0 protocol exerciser, negotiating a link to the maximum PCIe 6.0 data rate of 64 GT/s. They also effectively established a CXL 2.0 link to address future cache coherency in the datacenter.
The PCIe 6.0 specification introduces FLIT mode, where packets are organized in Flow Control Units of fixed sizes. Along with FLIT mode, PCIe 6.0 employs PAM4 signaling and forward error correction to achieve low latency, low complexity, and low bandwidth overhead.
Alphawave’s PCIe subsystem is a power-efficient, low-latency interface IP built off of its PAM4 SerDes IP. Using the silicon implementation of the PCIe 6.0 FLIT protocol, Keysight was able to successfully verify FLIT-mode transactions (requests and completions) of payload FLITs at 64 GT/s.
For more information about Alphawave’s PCIe and CXL IP portfolio, click here. Additional information about Keysight’s PCIe 6.0 protocol exerciser and analyzer can be found here.
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