How to tackle DRAM’s power conundrum
While DRAM designers strive for incremental improvements in performance, power, bit density, and capacity with each successive node, AI-driven data centers are putting a lot of pressure on memory makers to make further advances in power efficiency. Gary Hilson provides a sneak peek of how Micron—one of the three big DRAM producers—is reducing power consumption by employing high-K metal gate CMOS technology paired with design optimizations.
Read the full story at EDN’s sister publication, EE Times.
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