• Become a member
  • Log In
The Institution of Electronics
  • Home
  • About us
    • Our Objectives
    • Our History
    • Governance of the Institution
  • The Electron Magazine
    • 2024
      • 2024 – Winter
      • 2024 – Spring
      • 2024 – Summer
      • 2024 – Autumn
    • 2025
      • 2025 – Winter
      • 2025 – Spring
      • 2025 – Summer
      • 2025 – Autumn
    • 2026
      • 2026 – Winter
  • Members
    • Membership Grades and Fees
    • Members’ Resources
      • The Electron Newsletter
      • The Archives
  • Education and Projects
    • National Electronics Competition
    • Student Members’ Projects
    • Arkwright Engineering Scholarships
  • News
  • Contact Us
  • Menu Menu
Uncategorised

Bias for HF JFET

Junction field-effect transistors (JFETs) usually require some reverse bias voltage to be applied to a gate terminal.

In HF and UHF applications, this bias is often provided using the voltage across the source resistor Rs (Figure 1).

Figure 1: JFETs typically require some reverse bias across the gate terminal and in HF/UHF applications, this is often provided using the voltage across resistor Rs.

Wow the engineering world with your unique design: Design Ideas Submission Guide

Barring the evident lack of efficiency, such approach has other shortcomings as well:

The drain current has statistical dispersion, so to get a target value of the current some circuit adjustment is required.
The drain current may depend on temperature or power fluctuations.
To achieve an acceptable low source impedance, several capacitors Cs have to be used.
To maintain the same headroom a higher power voltage is required.
The lack of direct contact with the ground plane means worse cooling of the transistor, which is crucial for power applications.

The circuit in Figure 2 is free of all these. It consists of a control loop which produces control voltage of negative polarity for n-channel JFET amplifier.

Figure 2: A control loop that produces control voltage of negative polarity for n-channel JFET amplifier in HF and UHF applications.

The circuit uses two infrared LEDs IR333C (diameter = 5 mm) in a self-made photocoupler. Two such LEDs placed face-to-face in an appropriate PVC tube about 12 mm long, that’s all. One such device produces 0.81 V @ Iled < 4 mA, which is quite sufficient for the HEMT FHX35LG, for example.

Of course, if you need higher voltage, several such devices can be simply cascaded.

The main amplification in the loop is performed by the JFET itself. Its value is about gm * R1, where gm is a transconductance of Q1.

The transistor pair Q2 and Q3 compares the voltage drops on the resistors R1 and R2 making them equal. Hence, by changing the ratio R2:R3 you can set the working point you need:

Id = Vdd * R2 / ((R2 + R3) * R1)

As we can see, the drain current (Id) still depends on power voltage (Vdd). To avoid this dependence, we can replace resistor R2 with a Zener diode, then:

Id = Vz / R1

 —Peter Demchenko studied math at the University of Vilnius and has worked in software development.

 Related Content

JFET-based dc/dc converter operates from 300-mV supply
Input bias current of CMOS and JFET amplifiers
Your friend, the JFET
Discrete audio amplifier basics – Part 2: JFETs, MOSFETs and other circuit configurations
Adaptable pullup

<!–
googletag.cmd.push(function() { googletag.display(‘div-gpt-ad-native’); });
–>

The post Bias for HF JFET appeared first on EDN.

15 May 2024
http://institutionofelectronics.ac.uk/wp-content/uploads/2022/12/IOE_LOGO.png 0 0 http://institutionofelectronics.ac.uk/wp-content/uploads/2022/12/IOE_LOGO.png 2024-05-15 15:29:372024-05-15 15:29:37Bias for HF JFET

Latest news

  • Cheap and cheerful LMC555 RC PWM pulse generator12 August 2026 - 13:56
  • Record high wafer shipments. Can fabs keep pace?12 August 2026 - 07:51
  • Analog uncertainty-aware design: How it replaces Monte Carlo with certifiable yield intelligence11 August 2026 - 16:31
  • Automotive low side output switch architecture suitable for 8 to 48 volt buses and beyond11 August 2026 - 13:26
  • Inference 2.0: How enterprise AI is reshaping AI system architectures11 August 2026 - 07:19
  • Dissecting third-party camera batteries, part 2: Swelling10 August 2026 - 14:00
  • Component and layout rules for USB-C, PD, and CMTI10 August 2026 - 07:53
  • Bear on a power pole7 August 2026 - 13:46
  • Why software-defined systems require a dynamic data layer7 August 2026 - 10:42
  • Paper-based passives show impact of re-thinking substrate6 August 2026 - 16:22
IOE LOGO 2

Become a member

click here

Become a member

click here

Become a subscriber

click here

Become a sponsor

click here

© Copyright - The Institution of Electronics | Website by WHD Solutions
  • Link to LinkedIn
  • Link to Facebook
  • Link to X
Link to: Change of guard at Intel Foundry, again Link to: Change of guard at Intel Foundry, again Change of guard at Intel Foundry, again Link to: Thin PCBs: Challenges with BGA packages Link to: Thin PCBs: Challenges with BGA packages Thin PCBs: Challenges with BGA packages
Scroll to top Scroll to top Scroll to top