Independent control of thyristor half-wave firing angles via PWM
“Two halves make a whole” is a very old and often true maxim. For example, it’s almost always true when said about AC phase angle power control. You rarely want significant alternating half-cycle asymmetry due to the (usually undesirable) DC load current component that unequal half-cycle conduction angles create. A nicely balanced, DC-free, whole, and symmetrical full-wave power is therefore the desired output waveform.
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So, what to do if you have an application that needs better symmetry than available thyristors can deliver without some fine-tuning? For example, in Figure 1, Q2’s datasheet specifies ±3 V = ±8% of polarity-dependent trigger voltage asymmetry. Or suppose that (for some bizarre reason) you actually want precisely controllable amounts of deliberate half-cycle conduction angle inequality. What then?
Figure 1 offers a simple solution for both problems. It implements independent control of positive and negative half-cycle phase angles using separate and independent trigger-time constant-setting PWM channels: One for positive half cycles, another for negative. Where:
Positive half wave timeconstant = R1C1 / DF+
Negative half wave timeconstant = R1C1 / DF-
DF = PWM duty factor = 0 to 1
Figure 1 Q1 and Q3 provide independent triggering-time constants for opposite polarity half-waves.
The power control method in play is phase angle conduction via QUADRAC thyristor Q2. It’s wired in the traditional way except that opto-isolators Q1 and Q3 fill in for the usual manual phase adjustment pot. The duty factor (DF) of the PWM inputs sets the phototransistor’s average conductance. Diodes D1 and D2 select whichever optoisolator corresponds with an instantaneous 60-Hz half-wave polarity. The type H11D1 300-V opto has a typical current transfer ratio of 80% which makes ~10 mA of PWM drive current necessary. Current limiter R2’s 330 Ω assumes a 5-V rail and a low impedance driver. That will need adjustment if either assumption doesn’t apply to your system. The PWM cycle rate isn’t critical but should be circa 10 kHz.
The full-throttle output efficiency is around 99%, but Q2’s maximum junction temperature rating is only 110 °C. So, adequate heatsinking of Q2 will be wise if RMS output >200 W is expected.
The adjustment range for each half-cycle phase spans an upper limit of DF = 1, which sets a maximum conductance angle of ~2.6 radians and 95% = 117 Vrms output power, down to DF = 0 and zero power. Figure 2 shows the approximate relationship between DF and conduction angle, while Figure 3 illustrates its inverse.
Figure 2 Thyristor conduction angle R [R = pi – 0.60 DF-(2/pi)] versus PWM DF, where the y-axis is in radians and the x-axis is the unitless DF.
Figure 3 The PWM DF [((pi – R)/0.60)-(pi/2)] versus the desired conduction angle R. The y-axis is the DF, and the x-axis is in radians.
Stephen Woodward’s relationship with EDN’s DI column goes back quite a long way. Over 100 submissions have been accepted since his first contribution back in 1974.
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