Page 47 - Autumn 2024

Institution of Electronics News

WHY CHIPLETS ARE THE

FUTURE OF SILICON DESIGN

As Moore’s Law slows, traditional monolithic UCIe offers a low-latency, high-bandwidth, vendor-
chips are encountering significant limitations— neutral interface between chiplets, like what PCIe
physically, economically, and thermally. provided for circuit boards. With silicon interposers
and micro-bumps, die-to-die communication is now
Larger die sizes result in reduced yields and increased
approaching on-die speeds-essential for AI and HPC
costs, while placing logic, memory, and analog
workloads where data movement is a major factor in
circuits onto a single process node compromise both
power consumption. However, challenges persist.
performance and efficiency. This is why the industry is
shifting towards chiplets: compact, function-specific Thermal hotspots can develop when high-
dies that are integrated within a single package. This power chiplets are placed adjacent to sensitive
approach represents a more intelligent method for analog blocks. Maintaining signal integrity across
constructing systems. interconnects necessitates the co-design of circuits,
layouts, and packaging.
Chiplets let us mix and match technologies. Looking
for a state-of-the-art 3 nm CPU core? Combine it Additionally, EDA tools are still evolving to support
with a 22 nm analog I/O block or a specialized HBM multi-die system optimization. Nevertheless, the
memory stack-each designed on the most suitable benefits are evident. AMD’s EPYC CPUs, Intel’s Ponte
node. This heterogeneous integration enhances Vecchio GPUs, and next-generation automotive
performance per watt and significantly reduces costs SoCs all leverage chiplets to enhance performance
by improving yield: smaller dies are inherently less without the need to redesign entire dies. In edge
susceptible to being rendered unusable by a single devices, chiplets facilitate compact, power-efficient
defect. integration of AI accelerators, RF, and sensors-
increasingly important, on device intelligence.
Key facilitators such as 2.5D/3D packaging and
the UCIe (Universal Chiplet Interconnect Express) References: V. Gujar, “Chiplet Technology: Revolutionizing
Semiconductor Design,” IEEE Access, 2024. / UCIe Consortium, “The
standard enable this innovation.
UCIe Chiplet Interconnect Standard,” 2024.

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