TSMC adds two variants to 2-nm node, will Intel catch up?

TSMC’s 2-nm chip fabrication process, widely known as N2, is on track for production in 2025, according to the details provided by the company at its 2023 North America Technology Symposium in Santa Clara, California. Taiwan’s mega-fab will also add two variants to its N2 technology in 2026: N2P with backside power delivery and N2X for high-performance computing.

The N2 and its variants will be the first manufacturing nodes at TSMC to employ the gate-all-around (GAA) transistors—which TSMC calls nanosheet transistors—to boost performance, energy efficiency, and transistor densities for logic, SRAM, and analog circuits. The GAA technology facilitates lower leakage current as gates are present on all four sides of the channel. Moreover, GAA transistors boost the ability to adjust the channel width for higher performance or lower power consumption.

Figure 1 The announcement of two N2 variants was one of the most prominent highlights of the symposium. Source: TSMC

At the symposium, TSMC claimed that its new nanosheet transistors already meet 80% of the target performance specs, while the average yield of a 256-Mb SRAM is currently above 50%. And the semiconductor foundry still has two years to improve these figures.

According to TSMC, N2 will offer 10% to 15% more performance at the same power as N3 or a 25% to 20% power reduction at the same clocks. The fab also claims that for a mixed chip—comprising logic, SRAM and analog—N2 will accomplish 15% higher density than N3E, an enhanced version of the N3 fabrication node.

Figure 2 The symposium mostly provided details about N2 process node, which was announced last year. Source: TSMC

While the details about TSMC’s N2 technology have been seeping through for a while, what’s new is the announcement about the two new versions of the N2 fabrication node as this advanced fabrication technology extends into 2026. TSMC, which began researching the 2-nm chip fabrication process in 2020, has pursued this cutting-edge chip manufacturing technology relentlessly over the past years.

Below are some details about N2 fabrication node variants—N2P and N2X—which are expected to go into production in 2026, and the chips manufactured on these nodes will likely arrive in 2027.

N2P fabrication node

Earlier, when TSMC announced N2 production plans with a nanosheet design, it vowed to add backside power delivery to a future version; that version of 2-nm fabrication has been named N2P. It’s just like PowerVia and BSPDN fabrication technologies from Intel and Samsung, respectively, sandwiching transistors between the power delivery network and the signal network in order to improve transistor performance and reduce power consumption.

Backside power delivery, which decouples I/O and power wiring by moving power rails to the back, addresses challenges like elevated via resistances in the back-end-of-line (BEOL). So, at a time when chipmakers have been fighting resistances in chip power delivery circuitry, backside power delivery enhances transistor performance, reduces their power consumption, and eliminates some potential interference between data and power connections.

Applied Materials estimates that backside power delivery facilitates 20% to 30% logic cell area reductions. Though TSMC hasn’t provided any specifics about N2P technology, a report published in AnandTech claims that backside power rails could account for double-digit transistor density improvements and a single-digit efficiency boost.

N2X fabrication node

TSMC is also prepping N2X, a fabrication process tailored for high-performance computing (HPC) devices such as high-end CPUs and GPUs, which need higher voltages and clock speeds. N2X will come after N2P, so information is even more scarce about this N2 variant for HPC applications.

Will Intel catch up?

It’s worth mentioning here that Intel is following a similar trajectory for the 2-nm fabrication process on its 20A process, which also features backside power delivery technology. Intel is planning to take its 2-nm PowerVia fabrication node to volume production in late 2024, and if the Santa Clara, California-based chipmaker is able to execute that successfully, it will leave TSMC behind by nearly two years in the race for implementing backside power delivery.

However, that’s in question, given Intel’s track record in executing cutting-edge process nodes and its challenges in securing the latest extreme ultraviolet (EUV) lithography equipment from ASML. Nevertheless, TSMC has a second contender in the nanometer race besides Samsung.

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