TSMC upends 3-nm roadmap with three new nodes

TSMC’s 3-nm fabrication nodes mark the final generation of FinFET-based manufacturing processes as the foundry’s 2-nm process nodes will incorporate nanosheets, also known as gate-all-around (GAA) transistors. The mega-fab’s recent 2023 North America Technology Symposium provided ample information on the latest for 3-nm chip manufacturing process nodes.

The information about the baseline 3-nm node, N3, which is currently in production, and details about an enhanced version, N3E, to be launched in the second half of 2023, was made available last year. The N3 node features up to 25 extreme ultraviolet (EUV) layers while using double-patterning on some of them to facilitate higher logic and SRAM transistor density than TSMC’s N5 fabrication node.

On the other hand, N3E utilizes up to 19 EUV layers while not relying on EUV double patterning, which reduces fabrication complexity and costs. However, while N3E offers a wider process window and better yields, it provides lower logic density than N3. As a result, it’s less attractive for chip designs aiming for density and area gains.

Now TSMC is adding new variants to the N3 roadmap to further diversify the 3-nm process technology to meet chip designers’ diverse needs. Below is a brief outline of the three nodes TSMC unveiled at the symposium in Santa Clara, California: N3P, N3X and N3AE.

Figure 1 The 3-nm fabrication nodes have been diversified into a range of processes to meet the needs of a wide range of chips. Source: TSMC

N3P fabrication node

N3P, a refinement of N3E, lowers power consumption and bolsters performance and density by adjusting the optical performance of its scanners. In other words, it’s an optical shrink of N3E, providing 5% more speed at the same leakage, 5-10% power reduction at the same speed, and 1.04X more chip density.

N3P’s key objective is to optimize transistor density by building on N3E and improving transistor characteristics. TSMC claims that this 3-nm will boost transistor density by 4% for a mixed-chip design, which according to the foundry, is a chip consisting of 50% logic, 30% SRAM, and 20% analog circuits. N3P, projected to be one of TSMC’s most popular N3 nodes, will be available in the second half of 2024.

N3X fabrication node

N3X, tailored for high-performance computing devices like CPUs and GPUs, offers at least 5% higher clock speeds than N3P. While more tolerant of higher voltages, this node enables IC designers to crank up the clock speeds in exchange for higher overall leakage. According to TSMC, the N3X will support around 1.2 V, which is quite high for a 3-nm chip fabrication process.

N3X is a performance-focused node tailored for high-performance computing (HPC) processors for whom power leakage is less of an issue. These processors are commonly used in server-grade hardware with hefty cooling systems. Still, chip designers will have to make an effort to keep these power-hungry processors in check.

It’s also worth noting that N3X will offer the same transistor density as N3P, and its key value proposition is prioritizing performance and maximum clock frequencies for HPC applications. TSMC sources claim that N3X will be production ready in 2025. According to some industry insiders, Intel’s Celestial GPUs will be among the first to use the N3X fabrication node.

Figure 2 The N3P and N3X nodes diversify the fabrication process in terms of chip density and higher voltage tolerance, respectively. Source: TSMC

N3AE fabrication node

N3AE or “Auto Early” enables automotive applications on advanced chip manufacturing process technology. It offers automotive process design kits (PDKs) based on N3E and will be available in 2023. The fully automotive-qualified N3AE process will be unveiled in 2025.

Editor’s Note: This is part 1 of the blog series about TSMC’s new fabrication nodes and associated technologies. Part 2 will delve into TSMC’s roadmap for N2 process nodes.

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