Development environment builds RISC-V code

The Efinity RISC-V Embedded Software IDE from Efinix is an Eclipse-based integrated development environment (IDE) powered by Ashling’s RiscFree IDE. Efinity IDE offers intuitive development and debugging for the Efinix Sapphire RISC-V SoC. Through tight integration with Efinity design software, the new IDE provides an efficient way for designers to import projects created for the company’s Trion and Titanium FPGAs and rapidly develop embedded RISC-V code in a rich debug environment.

The Efinity RISC-V Embedded Software IDE is a turnkey package that brings enhanced debug to both bare-metal and FreeRTOS environments. Integration with Efinity projects delivers design flow automation for register-level debug of both control and status (CSR) and peripheral registers within the FPGA SoC. FreeRTOS task and queue lists provide application-level visibility. QEMU emulation support for 32-bit RISC-V cores, included in the IDE, enables SoC debug in the absence of target hardware.

“The Efinity RISC-V Embedded Software IDE delivers a truly intuitive design workflow for our best-in-class Sapphire RISC-V core,” said Jay Schleicher, Efinix SVP of Software Engineering. “Our collaboration with Ashling pairs the market leading development and debug environment with our efficient and disruptive FPGA technology to speed time to success in a wide range of embedded compute applications.”

Efinity RISC-V IDE product page


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